78002be334
* DSP: Own DSP RAM and add it to fastmem * Vendor Teakra * Add MacOS support to fastmem * Fix MacOS fastmem paths * Fix iOS build
688 lines
22 KiB
C++
688 lines
22 KiB
C++
#pragma once
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#include <algorithm>
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#include <array>
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#include <memory>
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#include <vector>
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#include "../../../src/common_types.h"
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#include "../../../src/crash.h"
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#include "../../../src/operand.h"
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namespace Teakra {
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struct RegisterState {
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void Reset() {
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*this = RegisterState();
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}
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/** Program control unit **/
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u32 pc = 0; // 18-bit, program counter
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u16 prpage = 0; // 4-bit, program page
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u16 cpc = 1; // 1-bit, change word order when push/pop pc
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u16 repc = 0; // 16-bit rep loop counter
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u16 repcs = 0; // repc shadow
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bool rep = false; // true when in rep loop
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u16 crep = 1; // 1-bit. If clear, store/restore repc to shadows on context switch
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u16 bcn = 0; // 3-bit, nest loop counter
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u16 lp = 0; // 1-bit, set when in a loop
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struct BlockRepeatFrame {
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u32 start = 0;
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u32 end = 0;
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u16 lc = 0;
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};
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std::array<BlockRepeatFrame, 4> bkrep_stack;
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u16& Lc() {
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if (lp)
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return bkrep_stack[bcn - 1].lc;
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return bkrep_stack[0].lc;
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}
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/** Computation unit **/
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// 40-bit 2's comp accumulators.
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// Use 64-bit 2's comp here. The upper 24 bits are always sign extension
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std::array<u64, 2> a{};
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std::array<u64, 2> b{};
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u64 a1s = 0, b1s = 0; // shadows for a1 and b1
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u16 ccnta = 1; // 1-bit. If clear, store/restore a1/b1 to shadows on context switch
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u16 sat = 0; // 1-bit, disable saturation when moving from acc
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u16 sata = 1; // 1-bit, disable saturation when moving to acc
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u16 s = 0; // 1-bit, shift mode. 0 - arithmetic, 1 - logic
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u16 sv = 0; // 16-bit two's complement shift value
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// 1-bit flags
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u16 fz = 0; // zero flag
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u16 fm = 0; // negative flag
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u16 fn = 0; // normalized flag
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u16 fv = 0; // overflow flag
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u16 fe = 0; // extension flag
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u16 fc0 = 0; // carry flag
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u16 fc1 = 0; // another carry flag
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u16 flm = 0; // set on saturation
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u16 fvl = 0; // latching fv
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u16 fr = 0; // Rn zero flag
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// Viterbi
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u16 vtr0 = 0;
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u16 vtr1 = 0;
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/** Multiplication unit **/
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std::array<u16, 2> x{}; // factor
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std::array<u16, 2> y{}; // factor
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u16 hwm = 0; // 2-bit, half word mode, modify y on multiplication
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std::array<u32, 2> p{}; // product
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std::array<u16, 2> pe{}; // 1-bit product extension
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std::array<u16, 2> ps{}; // 2-bit, product shift mode
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u16 p0h_cbs = 0; // 16-bit hidden state for codebook search (CBS) opcode
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/** Address unit **/
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std::array<u16, 8> r{}; // 16-bit general and address registers
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u16 mixp = 0; // 16-bit, stores result of min/max instructions
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u16 sp = 0; // 16-bit stack pointer
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u16 page = 0; // 8-bit, higher part of MemImm8 address
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u16 pcmhi = 0; // 2-bit, higher part of program address for movp/movd
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// shadows for bank exchange;
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u16 r0b = 0, r1b = 0, r4b = 0, r7b = 0;
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/** Address step/mod unit **/
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// step/modulo
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u16 stepi = 0, stepj = 0; // 7-bit step
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u16 modi = 0, modj = 0; // 9-bit mod
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u16 stepi0 = 0, stepj0 = 0; // 16-bit step
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// shadows for bank exchange
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u16 stepib = 0, stepjb = 0;
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u16 modib = 0, modjb = 0;
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u16 stepi0b = 0, stepj0b = 0;
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std::array<u16, 8> m{}; // 1-bit each, enable modulo arithmetic for Rn
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std::array<u16, 8> br{}; // 1-bit each, use bit-reversed value from Rn as address
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u16 stp16 = 0; // 1 bit. If set, stepi0/j0 will be exchanged along with cfgi/j in banke, and use
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// stepi0/j0 for steping
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u16 cmd = 1; // 1-bit, step/mod method. 0 - Teak; 1 - TeakLite
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u16 epi = 0; // 1-bit. If set, cause r3 = 0 when steping r3
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u16 epj = 0; // 1-bit. If set, cause r7 = 0 when steping r7
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/** Indirect address unit **/
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// 3 bits each
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// 0: +0
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// 1: +1
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// 2: -1
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// 3: +s
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// 4: +2
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// 5: -2
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// 6: +2*
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// 7: -2*
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std::array<u16, 4> arstep{{1, 4, 5, 3}}, arpstepi{{1, 4, 5, 3}}, arpstepj{{1, 4, 5, 3}};
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// 2 bits each
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// 0: +0
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// 1: +1
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// 2: -1
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// 3: -1*
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std::array<u16, 4> aroffset{{0, 1, 2, 0}}, arpoffseti{{0, 1, 2, 0}}, arpoffsetj{{0, 1, 2, 0}};
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// 3 bits each, represent r0~r7
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std::array<u16, 4> arrn{{0, 4, 2, 6}};
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// 2 bits each. for i represent r0~r3, for j represents r4~r7
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std::array<u16, 4> arprni{{0, 1, 2, 3}}, arprnj{{0, 1, 2, 3}};
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/** Interrupt unit **/
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// interrupt pending bit
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std::array<u16, 3> ip{};
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u16 ipv = 0;
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// interrupt enable bit
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std::array<u16, 3> im{};
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u16 imv = 0;
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// interrupt context switching bit
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std::array<u16, 3> ic{};
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u16 nimc = 0;
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// interrupt enable master bit
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u16 ie = 0;
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/** Extension unit **/
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std::array<u16, 5> ou{}; // user output pins
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std::array<u16, 2> iu{}; // user input pins
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std::array<u16, 4> ext{};
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u16 mod0_unk_const = 1; // 3-bit
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/** Shadow registers **/
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template <u16 RegisterState::* origin>
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class ShadowRegister {
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public:
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void Store(RegisterState* self) {
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shadow = self->*origin;
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}
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void Restore(RegisterState* self) {
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self->*origin = shadow;
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}
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private:
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u16 shadow = 0;
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};
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template <std::size_t size, std::array<u16, size> RegisterState::* origin>
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class ShadowArrayRegister {
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public:
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void Store(RegisterState* self) {
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shadow = self->*origin;
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}
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void Restore(RegisterState* self) {
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self->*origin = shadow;
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}
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private:
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std::array<u16, size> shadow{};
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};
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template <typename... ShadowRegisters>
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class ShadowRegisterList : private ShadowRegisters... {
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public:
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void Store(RegisterState* self) {
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(ShadowRegisters::Store(self), ...);
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}
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void Restore(RegisterState* self) {
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(ShadowRegisters::Restore(self), ...);
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}
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};
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template <u16 RegisterState::* origin>
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class ShadowSwapRegister {
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public:
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void Swap(RegisterState* self) {
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std::swap(self->*origin, shadow);
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}
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private:
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u16 shadow = 0;
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};
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template <std::size_t size, std::array<u16, size> RegisterState::* origin>
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class ShadowSwapArrayRegister {
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public:
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void Swap(RegisterState* self) {
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std::swap(self->*origin, shadow);
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}
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private:
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std::array<u16, size> shadow{};
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};
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template <typename... ShadowSwapRegisters>
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class ShadowSwapRegisterList : private ShadowSwapRegisters... {
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public:
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void Swap(RegisterState* self) {
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(ShadowSwapRegisters::Swap(self), ...);
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}
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};
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// clang-format off
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ShadowRegisterList<
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ShadowRegister<&RegisterState::flm>,
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ShadowRegister<&RegisterState::fvl>,
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ShadowRegister<&RegisterState::fe>,
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ShadowRegister<&RegisterState::fc0>,
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ShadowRegister<&RegisterState::fc1>,
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ShadowRegister<&RegisterState::fv>,
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ShadowRegister<&RegisterState::fn>,
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ShadowRegister<&RegisterState::fm>,
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ShadowRegister<&RegisterState::fz>,
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ShadowRegister<&RegisterState::fr>
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> shadow_registers;
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ShadowSwapRegisterList<
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ShadowSwapRegister<&RegisterState::pcmhi>,
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ShadowSwapRegister<&RegisterState::sat>,
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ShadowSwapRegister<&RegisterState::sata>,
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ShadowSwapRegister<&RegisterState::hwm>,
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ShadowSwapRegister<&RegisterState::s>,
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ShadowSwapArrayRegister<2, &RegisterState::ps>,
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ShadowSwapRegister<&RegisterState::page>,
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ShadowSwapRegister<&RegisterState::stp16>,
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ShadowSwapRegister<&RegisterState::cmd>,
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ShadowSwapArrayRegister<8, &RegisterState::m>,
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ShadowSwapArrayRegister<8, &RegisterState::br>,
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ShadowSwapArrayRegister<3, &RegisterState::im>, // ?
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ShadowSwapRegister<&RegisterState::imv>, // ?
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ShadowSwapRegister<&RegisterState::epi>,
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ShadowSwapRegister<&RegisterState::epj>
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> shadow_swap_registers;
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// clang-format on
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template <unsigned index>
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class ShadowSwapAr {
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public:
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void Swap(RegisterState* self) {
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std::swap(self->arrn[index * 2], rni);
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std::swap(self->arrn[index * 2 + 1], rnj);
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std::swap(self->arstep[index * 2], stepi);
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std::swap(self->arstep[index * 2 + 1], stepj);
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std::swap(self->aroffset[index * 2], offseti);
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std::swap(self->aroffset[index * 2 + 1], offsetj);
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}
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private:
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u16 rni, rnj, stepi, stepj, offseti, offsetj;
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};
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template <unsigned index>
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class ShadowSwapArp {
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public:
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void Swap(RegisterState* self) {
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std::swap(self->arprni[index], rni);
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std::swap(self->arprnj[index], rnj);
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std::swap(self->arpstepi[index], stepi);
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std::swap(self->arpstepj[index], stepj);
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std::swap(self->arpoffseti[index], offseti);
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std::swap(self->arpoffsetj[index], offsetj);
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}
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private:
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u16 rni, rnj, stepi, stepj, offseti, offsetj;
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};
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ShadowSwapAr<0> shadow_swap_ar0;
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ShadowSwapAr<1> shadow_swap_ar1;
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ShadowSwapArp<0> shadow_swap_arp0;
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ShadowSwapArp<1> shadow_swap_arp1;
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ShadowSwapArp<2> shadow_swap_arp2;
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ShadowSwapArp<3> shadow_swap_arp3;
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void ShadowStore() {
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shadow_registers.Store(this);
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}
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void ShadowRestore() {
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shadow_registers.Restore(this);
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}
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void SwapAllArArp() {
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shadow_swap_ar0.Swap(this);
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shadow_swap_ar1.Swap(this);
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shadow_swap_arp0.Swap(this);
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shadow_swap_arp1.Swap(this);
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shadow_swap_arp2.Swap(this);
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shadow_swap_arp3.Swap(this);
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}
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void ShadowSwap() {
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shadow_swap_registers.Swap(this);
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SwapAllArArp();
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}
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void SwapAr(u16 index) {
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switch (index) {
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case 0:
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shadow_swap_ar0.Swap(this);
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break;
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case 1:
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shadow_swap_ar1.Swap(this);
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break;
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}
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}
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void SwapArp(u16 index) {
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switch (index) {
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case 0:
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shadow_swap_arp0.Swap(this);
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break;
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case 1:
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shadow_swap_arp1.Swap(this);
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break;
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case 2:
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shadow_swap_arp2.Swap(this);
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break;
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case 3:
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shadow_swap_arp3.Swap(this);
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break;
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}
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}
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bool ConditionPass(Cond cond) const {
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switch (cond.GetName()) {
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case CondValue::True:
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return true;
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case CondValue::Eq:
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return fz == 1;
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case CondValue::Neq:
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return fz == 0;
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case CondValue::Gt:
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return fz == 0 && fm == 0;
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case CondValue::Ge:
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return fm == 0;
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case CondValue::Lt:
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return fm == 1;
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case CondValue::Le:
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return fm == 1 || fz == 1;
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case CondValue::Nn:
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return fn == 0;
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case CondValue::C:
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return fc0 == 1;
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case CondValue::V:
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return fv == 1;
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case CondValue::E:
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return fe == 1;
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case CondValue::L:
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return flm == 1 || fvl == 1;
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case CondValue::Nr:
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return fr == 0;
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case CondValue::Niu0:
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return iu[0] == 0;
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case CondValue::Iu0:
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return iu[0] == 1;
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case CondValue::Iu1:
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return iu[1] == 1;
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default:
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UNREACHABLE();
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}
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}
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template <typename PseudoRegisterT>
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u16 Get() const {
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return PseudoRegisterT::Get(this);
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}
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template <typename PseudoRegisterT>
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void Set(u16 value) {
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PseudoRegisterT::Set(this, value);
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}
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};
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template <u16 RegisterState::* target>
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struct Redirector {
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static u16 Get(const RegisterState* self) {
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return self->*target;
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}
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static void Set(RegisterState* self, u16 value) {
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self->*target = value;
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}
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};
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template <std::size_t size, std::array<u16, size> RegisterState::* target, std::size_t index>
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struct ArrayRedirector {
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static u16 Get(const RegisterState* self) {
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return (self->*target)[index];
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}
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static void Set(RegisterState* self, u16 value) {
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(self->*target)[index] = value;
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}
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};
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template <u16 RegisterState::* target0, u16 RegisterState::* target1>
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struct DoubleRedirector {
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static u16 Get(const RegisterState* self) {
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return self->*target0 | self->*target1;
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}
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static void Set(RegisterState* self, u16 value) {
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self->*target0 = self->*target1 = value;
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}
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};
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template <u16 RegisterState::* target>
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struct RORedirector {
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static u16 Get(const RegisterState* self) {
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return self->*target;
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}
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static void Set(RegisterState*, u16) {
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// no
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}
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};
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template <std::size_t size, std::array<u16, size> RegisterState::* target, std::size_t index>
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struct ArrayRORedirector {
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static u16 Get(const RegisterState* self) {
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return (self->*target)[index];
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}
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static void Set(RegisterState*, u16) {
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// no
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}
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};
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template <unsigned index>
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struct AccEProxy {
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static u16 Get(const RegisterState* self) {
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return (u16)((self->a[index] >> 32) & 0xF);
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}
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static void Set(RegisterState* self, u16 value) {
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u32 value32 = SignExtend<4>((u32)value);
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self->a[index] &= 0xFFFFFFFF;
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self->a[index] |= (u64)value32 << 32;
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}
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};
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struct LPRedirector {
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static u16 Get(const RegisterState* self) {
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return self->lp;
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}
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static void Set(RegisterState* self, u16 value) {
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if (value != 0) {
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self->lp = 0;
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self->bcn = 0;
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}
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}
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};
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template <typename Proxy, unsigned position, unsigned length>
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struct ProxySlot {
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using proxy = Proxy;
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static constexpr unsigned pos = position;
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static constexpr unsigned len = length;
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static_assert(length < 16, "Error");
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static_assert(position + length <= 16, "Error");
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static constexpr u16 mask = ((1 << length) - 1) << position;
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};
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template <typename... ProxySlots>
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struct PseudoRegister {
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static_assert(NoOverlap<u16, ProxySlots::mask...>, "Error");
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static u16 Get(const RegisterState* self) {
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return ((ProxySlots::proxy::Get(self) << ProxySlots::pos) | ...);
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}
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static void Set(RegisterState* self, u16 value) {
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(ProxySlots::proxy::Set(self, (value >> ProxySlots::pos) & ((1 << ProxySlots::len) - 1)),
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...);
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}
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};
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// clang-format off
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using cfgi = PseudoRegister<
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ProxySlot<Redirector<&RegisterState::stepi>, 0, 7>,
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ProxySlot<Redirector<&RegisterState::modi>, 7, 9>
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>;
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using cfgj = PseudoRegister<
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ProxySlot<Redirector<&RegisterState::stepj>, 0, 7>,
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ProxySlot<Redirector<&RegisterState::modj>, 7, 9>
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>;
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using stt0 = PseudoRegister<
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ProxySlot<Redirector<&RegisterState::flm>, 0, 1>,
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ProxySlot<Redirector<&RegisterState::fvl>, 1, 1>,
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ProxySlot<Redirector<&RegisterState::fe>, 2, 1>,
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ProxySlot<Redirector<&RegisterState::fc0>, 3, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fv>, 4, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fn>, 5, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fm>, 6, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fz>, 7, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fc1>, 11, 1>
|
|
>;
|
|
using stt1 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::fr>, 4, 1>,
|
|
ProxySlot<ArrayRORedirector<2, &RegisterState::iu, 0>, 10, 1>,
|
|
ProxySlot<ArrayRORedirector<2, &RegisterState::iu, 1>, 11, 1>,
|
|
ProxySlot<ArrayRedirector<2, &RegisterState::pe, 0>, 14, 1>,
|
|
ProxySlot<ArrayRedirector<2, &RegisterState::pe, 1>, 15, 1>
|
|
>;
|
|
using stt2 = PseudoRegister<
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 0>, 0, 1>,
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 1>, 1, 1>,
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 2>, 2, 1>,
|
|
ProxySlot<RORedirector<&RegisterState::ipv>, 3, 1>,
|
|
|
|
ProxySlot<Redirector<&RegisterState::pcmhi>, 6, 2>,
|
|
|
|
ProxySlot<RORedirector<&RegisterState::bcn>, 12, 3>,
|
|
ProxySlot<LPRedirector, 15, 1>
|
|
>;
|
|
using mod0 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::sat>, 0, 1>,
|
|
ProxySlot<Redirector<&RegisterState::sata>, 1, 1>,
|
|
ProxySlot<RORedirector<&RegisterState::mod0_unk_const>, 2, 3>,
|
|
ProxySlot<Redirector<&RegisterState::hwm>, 5, 2>,
|
|
ProxySlot<Redirector<&RegisterState::s>, 7, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 0>, 8, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 1>, 9, 1>,
|
|
ProxySlot<ArrayRedirector<2, &RegisterState::ps, 0>, 10, 2>,
|
|
|
|
ProxySlot<ArrayRedirector<2, &RegisterState::ps, 1>, 13, 2>
|
|
>;
|
|
using mod1 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::page>, 0, 8>,
|
|
|
|
ProxySlot<Redirector<&RegisterState::stp16>, 12, 1>,
|
|
ProxySlot<Redirector<&RegisterState::cmd>, 13, 1>,
|
|
ProxySlot<Redirector<&RegisterState::epi>, 14, 1>,
|
|
ProxySlot<Redirector<&RegisterState::epj>, 15, 1>
|
|
>;
|
|
using mod2 = PseudoRegister<
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 0>, 0, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 1>, 1, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 2>, 2, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 3>, 3, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 4>, 4, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 5>, 5, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 6>, 6, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 7>, 7, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 0>, 8, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 1>, 9, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 2>, 10, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 3>, 11, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 4>, 12, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 5>, 13, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 6>, 14, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::br, 7>, 15, 1>
|
|
>;
|
|
using mod3 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::nimc>, 0, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 0>, 1, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 1>, 2, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 2>, 3, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 2>, 4, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 3>, 5, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 4>, 6, 1>,
|
|
ProxySlot<Redirector<&RegisterState::ie>, 7, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 0>, 8, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 1>, 9, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 2>, 10, 1>,
|
|
ProxySlot<Redirector<&RegisterState::imv>, 11, 1>,
|
|
|
|
ProxySlot<Redirector<&RegisterState::ccnta>, 13, 1>,
|
|
ProxySlot<Redirector<&RegisterState::cpc>, 14, 1>,
|
|
ProxySlot<Redirector<&RegisterState::crep>, 15, 1>
|
|
>;
|
|
|
|
using st0 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::sat>, 0, 1>,
|
|
ProxySlot<Redirector<&RegisterState::ie>, 1, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 0>, 2, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 1>, 3, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fr>, 4, 1>,
|
|
ProxySlot<DoubleRedirector<&RegisterState::flm, &RegisterState::fvl>, 5, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fe>, 6, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fc0>, 7, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fv>, 8, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fn>, 9, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fm>, 10, 1>,
|
|
ProxySlot<Redirector<&RegisterState::fz>, 11, 1>,
|
|
ProxySlot<AccEProxy<0>, 12, 4>
|
|
>;
|
|
using st1 = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::page>, 0, 8>,
|
|
// 8, 9: reserved
|
|
ProxySlot<ArrayRedirector<2, &RegisterState::ps, 0>, 10, 2>,
|
|
ProxySlot<AccEProxy<1>, 12, 4>
|
|
>;
|
|
using st2 = PseudoRegister<
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 0>, 0, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 1>, 1, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 2>, 2, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 3>, 3, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 4>, 4, 1>,
|
|
ProxySlot<ArrayRedirector<8, &RegisterState::m, 5>, 5, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::im, 2>, 6, 1>,
|
|
ProxySlot<Redirector<&RegisterState::s>, 7, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 0>, 8, 1>,
|
|
ProxySlot<ArrayRedirector<5, &RegisterState::ou, 1>, 9, 1>,
|
|
ProxySlot<ArrayRORedirector<2, &RegisterState::iu, 0>, 10, 1>,
|
|
ProxySlot<ArrayRORedirector<2, &RegisterState::iu, 1>, 11, 1>,
|
|
// 12: reserved
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 2>, 13, 1>, // Note the index order!
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 0>, 14, 1>,
|
|
ProxySlot<ArrayRORedirector<3, &RegisterState::ip, 1>, 15, 1>
|
|
>;
|
|
using icr = PseudoRegister<
|
|
ProxySlot<Redirector<&RegisterState::nimc>, 0, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 0>, 1, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 1>, 2, 1>,
|
|
ProxySlot<ArrayRedirector<3, &RegisterState::ic, 2>, 3, 1>,
|
|
ProxySlot<LPRedirector, 4, 1>,
|
|
ProxySlot<RORedirector<&RegisterState::bcn>, 5, 3>
|
|
>;
|
|
|
|
template<unsigned index>
|
|
using ar = PseudoRegister<
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arstep, index * 2 + 1>, 0, 3>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::aroffset, index * 2 + 1>, 3, 2>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arstep, index * 2>, 5, 3>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::aroffset, index * 2>, 8, 2>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arrn, index * 2 + 1>, 10, 3>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arrn, index * 2>, 13, 3>
|
|
>;
|
|
|
|
using ar0 = ar<0>;
|
|
using ar1 = ar<1>;
|
|
|
|
template<unsigned index>
|
|
using arp = PseudoRegister<
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arpstepi, index>, 0, 3>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arpoffseti, index>, 3, 2>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arpstepj, index>, 5, 3>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arpoffsetj, index>, 8, 2>,
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arprni, index>, 10, 2>,
|
|
// bit 12 reserved
|
|
ProxySlot<ArrayRedirector<4, &RegisterState::arprnj, index>, 13, 2>
|
|
// bit 15 reserved
|
|
>;
|
|
|
|
using arp0 = arp<0>;
|
|
using arp1 = arp<1>;
|
|
using arp2 = arp<2>;
|
|
using arp3 = arp<3>;
|
|
|
|
// clang-format on
|
|
|
|
} // namespace Teakra
|