acaca4188e
* gdbstub: fix IsMemoryBreak() returning false while connected to client As a result, the only existing codepath for a memory watchpoint hit to break into GDB (InterpeterMainLoop, GDB_BP_CHECK, ARMul_State::RecordBreak) is finally taken, which exposes incorrect logic* in both RecordBreak and ServeBreak. * a blank BreakpointAddress structure is passed, which sets r15 (PC) to NULL * gdbstub: DynCom: default-initialize two members/vars used in conditionals * gdbstub: DynCom: don't record memory watchpoint hits via RecordBreak() For now, instead check for GDBStub::IsMemoryBreak() in InterpreterMainLoop and ServeBreak. Fixes PC being set to a stale/unhit breakpoint address (often zero) when a memory watchpoint (rwatch, watch, awatch) is handled in ServeBreak() and generates a GDB trap. Reasons for removing a call to RecordBreak() for memory watchpoints: * The``breakpoint_data`` we pass is typed Execute or None. It describes the predicted next code breakpoint hit relative to PC; * GDBStub::IsMemoryBreak() returns true if a recent Read/Write operation hit a watchpoint. It doesn't specify which in return, nor does it trace it anywhere. Thus, the only data we could give RecordBreak() is a placeholder BreakpointAddress at offset NULL and type Access. I found the idea silly, compared to simply relying on GDBStub::IsMemoryBreak(). There is currently no measure in the code that remembers the addresses (and types) of any watchpoints that were hit by an instruction, in order to send them to GDB as "extended stop information." I'm considering an implementation for this. * gdbstub: Change an ASSERT to DEBUG_ASSERT I have never seen the (Reg[15] == last_bkpt.address) assert fail in practice, even after several weeks of (locally) developping various branches around GDB. Only leave it inside Debug builds.
619 lines
21 KiB
C++
619 lines
21 KiB
C++
// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include "common/logging/log.h"
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#include "common/swap.h"
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/core.h"
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#include "core/memory.h"
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ARMul_State::ARMul_State(Core::System* system, Memory::MemorySystem& memory,
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PrivilegeMode initial_mode)
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: system(system), memory(memory) {
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Reset();
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ChangePrivilegeMode(initial_mode);
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}
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void ARMul_State::ChangePrivilegeMode(u32 new_mode) {
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if (Mode == new_mode)
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return;
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if (new_mode != USERBANK) {
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switch (Mode) {
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case SYSTEM32MODE: // Shares registers with user mode
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case USER32MODE:
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Reg_usr[0] = Reg[13];
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Reg_usr[1] = Reg[14];
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break;
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case IRQ32MODE:
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Reg_irq[0] = Reg[13];
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Reg_irq[1] = Reg[14];
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Spsr[IRQBANK] = Spsr_copy;
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break;
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case SVC32MODE:
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Reg_svc[0] = Reg[13];
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Reg_svc[1] = Reg[14];
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Spsr[SVCBANK] = Spsr_copy;
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break;
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case ABORT32MODE:
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Reg_abort[0] = Reg[13];
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Reg_abort[1] = Reg[14];
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Spsr[ABORTBANK] = Spsr_copy;
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break;
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case UNDEF32MODE:
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Reg_undef[0] = Reg[13];
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Reg_undef[1] = Reg[14];
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Spsr[UNDEFBANK] = Spsr_copy;
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break;
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case FIQ32MODE:
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std::copy(Reg.begin() + 8, Reg.end() - 1, Reg_firq.begin());
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Spsr[FIQBANK] = Spsr_copy;
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break;
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}
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switch (new_mode) {
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case USER32MODE:
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Reg[13] = Reg_usr[0];
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Reg[14] = Reg_usr[1];
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Bank = USERBANK;
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break;
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case IRQ32MODE:
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Reg[13] = Reg_irq[0];
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Reg[14] = Reg_irq[1];
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Spsr_copy = Spsr[IRQBANK];
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Bank = IRQBANK;
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break;
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case SVC32MODE:
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Reg[13] = Reg_svc[0];
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Reg[14] = Reg_svc[1];
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Spsr_copy = Spsr[SVCBANK];
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Bank = SVCBANK;
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break;
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case ABORT32MODE:
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Reg[13] = Reg_abort[0];
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Reg[14] = Reg_abort[1];
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Spsr_copy = Spsr[ABORTBANK];
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Bank = ABORTBANK;
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break;
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case UNDEF32MODE:
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Reg[13] = Reg_undef[0];
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Reg[14] = Reg_undef[1];
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Spsr_copy = Spsr[UNDEFBANK];
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Bank = UNDEFBANK;
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break;
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case FIQ32MODE:
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std::copy(Reg_firq.begin(), Reg_firq.end(), Reg.begin() + 8);
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Spsr_copy = Spsr[FIQBANK];
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Bank = FIQBANK;
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break;
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case SYSTEM32MODE: // Shares registers with user mode.
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Reg[13] = Reg_usr[0];
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Reg[14] = Reg_usr[1];
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Bank = SYSTEMBANK;
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break;
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}
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// Set the mode bits in the APSR
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Cpsr = (Cpsr & ~Mode) | new_mode;
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Mode = new_mode;
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}
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}
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// Performs a reset
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void ARMul_State::Reset() {
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VFPInit(this);
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// Set stack pointer to the top of the stack
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Reg[13] = 0x10000000;
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Reg[15] = 0;
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Cpsr = INTBITS | SVC32MODE;
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Mode = SVC32MODE;
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Bank = SVCBANK;
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ResetMPCoreCP15Registers();
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NresetSig = HIGH;
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NfiqSig = HIGH;
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NirqSig = HIGH;
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NtransSig = (Mode & 3) ? HIGH : LOW;
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abortSig = LOW;
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NumInstrs = 0;
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Emulate = RUN;
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}
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// Resets certain MPCore CP15 values to their ARM-defined reset values.
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void ARMul_State::ResetMPCoreCP15Registers() {
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// c0
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CP15[CP15_MAIN_ID] = 0x410FB024;
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CP15[CP15_TLB_TYPE] = 0x00000800;
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CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
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CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
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CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
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CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
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CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
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CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
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CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
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CP15[CP15_ISA_FEATURE_0] = 0x00100011;
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CP15[CP15_ISA_FEATURE_1] = 0x12002111;
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CP15[CP15_ISA_FEATURE_2] = 0x11221011;
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CP15[CP15_ISA_FEATURE_3] = 0x01102131;
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CP15[CP15_ISA_FEATURE_4] = 0x00000141;
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// c1
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CP15[CP15_CONTROL] = 0x00054078;
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CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
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CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
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// c2
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CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
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CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
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CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
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// c3
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CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
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// c7
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CP15[CP15_PHYS_ADDRESS] = 0x00000000;
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// c9
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CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
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// c10
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CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
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CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
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CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
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// c13
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CP15[CP15_PID] = 0x00000000;
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CP15[CP15_CONTEXT_ID] = 0x00000000;
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CP15[CP15_THREAD_UPRW] = 0x00000000;
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CP15[CP15_THREAD_URO] = 0x00000000;
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CP15[CP15_THREAD_PRW] = 0x00000000;
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// c15
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CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
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CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
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CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
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CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
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CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
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}
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static void CheckMemoryBreakpoint(u32 address, GDBStub::BreakpointType type) {
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if (GDBStub::IsServerEnabled() && GDBStub::CheckBreakpoint(address, type)) {
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LOG_DEBUG(Debug, "Found memory breakpoint @ {:08x}", address);
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GDBStub::Break(true);
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}
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}
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u8 ARMul_State::ReadMemory8(u32 address) const {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
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return memory.Read8(address);
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}
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u16 ARMul_State::ReadMemory16(u32 address) const {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
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u16 data = memory.Read16(address);
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if (InBigEndianMode())
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data = Common::swap16(data);
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return data;
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}
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u32 ARMul_State::ReadMemory32(u32 address) const {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
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u32 data = memory.Read32(address);
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if (InBigEndianMode())
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data = Common::swap32(data);
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return data;
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}
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u64 ARMul_State::ReadMemory64(u32 address) const {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
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u64 data = memory.Read64(address);
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if (InBigEndianMode())
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data = Common::swap64(data);
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return data;
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}
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void ARMul_State::WriteMemory8(u32 address, u8 data) {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
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memory.Write8(address, data);
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}
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void ARMul_State::WriteMemory16(u32 address, u16 data) {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
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if (InBigEndianMode())
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data = Common::swap16(data);
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memory.Write16(address, data);
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}
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void ARMul_State::WriteMemory32(u32 address, u32 data) {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
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if (InBigEndianMode())
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data = Common::swap32(data);
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memory.Write32(address, data);
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}
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void ARMul_State::WriteMemory64(u32 address, u64 data) {
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CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
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if (InBigEndianMode())
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data = Common::swap64(data);
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memory.Write64(address, data);
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}
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// Reads from the CP15 registers. Used with implementation of the MRC instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const {
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// Unprivileged registers
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if (crn == 13 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 2)
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return CP15[CP15_THREAD_UPRW];
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if (opcode_2 == 3)
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return CP15[CP15_THREAD_URO];
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}
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if (InAPrivilegedMode()) {
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if (crn == 0 && opcode_1 == 0) {
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if (crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_MAIN_ID];
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if (opcode_2 == 1)
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return CP15[CP15_CACHE_TYPE];
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if (opcode_2 == 3)
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return CP15[CP15_TLB_TYPE];
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if (opcode_2 == 5)
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return CP15[CP15_CPU_ID];
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} else if (crm == 1) {
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if (opcode_2 == 0)
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return CP15[CP15_PROCESSOR_FEATURE_0];
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if (opcode_2 == 1)
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return CP15[CP15_PROCESSOR_FEATURE_1];
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if (opcode_2 == 2)
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return CP15[CP15_DEBUG_FEATURE_0];
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if (opcode_2 == 4)
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return CP15[CP15_MEMORY_MODEL_FEATURE_0];
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if (opcode_2 == 5)
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return CP15[CP15_MEMORY_MODEL_FEATURE_1];
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if (opcode_2 == 6)
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return CP15[CP15_MEMORY_MODEL_FEATURE_2];
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if (opcode_2 == 7)
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return CP15[CP15_MEMORY_MODEL_FEATURE_3];
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} else if (crm == 2) {
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if (opcode_2 == 0)
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return CP15[CP15_ISA_FEATURE_0];
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if (opcode_2 == 1)
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return CP15[CP15_ISA_FEATURE_1];
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if (opcode_2 == 2)
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return CP15[CP15_ISA_FEATURE_2];
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if (opcode_2 == 3)
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return CP15[CP15_ISA_FEATURE_3];
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if (opcode_2 == 4)
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return CP15[CP15_ISA_FEATURE_4];
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}
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}
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if (crn == 1 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_CONTROL];
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if (opcode_2 == 1)
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return CP15[CP15_AUXILIARY_CONTROL];
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if (opcode_2 == 2)
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return CP15[CP15_COPROCESSOR_ACCESS_CONTROL];
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}
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if (crn == 2 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_TRANSLATION_BASE_TABLE_0];
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if (opcode_2 == 1)
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return CP15[CP15_TRANSLATION_BASE_TABLE_1];
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if (opcode_2 == 2)
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return CP15[CP15_TRANSLATION_BASE_CONTROL];
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}
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if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return CP15[CP15_DOMAIN_ACCESS_CONTROL];
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if (crn == 5 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_FAULT_STATUS];
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if (opcode_2 == 1)
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return CP15[CP15_INSTR_FAULT_STATUS];
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}
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if (crn == 6 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_FAULT_ADDRESS];
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if (opcode_2 == 1)
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return CP15[CP15_WFAR];
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}
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if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
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return CP15[CP15_PHYS_ADDRESS];
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if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return CP15[CP15_DATA_CACHE_LOCKDOWN];
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if (crn == 10 && opcode_1 == 0) {
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if (crm == 0 && opcode_2 == 0)
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return CP15[CP15_TLB_LOCKDOWN];
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if (crm == 2) {
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if (opcode_2 == 0)
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return CP15[CP15_PRIMARY_REGION_REMAP];
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if (opcode_2 == 1)
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return CP15[CP15_NORMAL_REGION_REMAP];
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}
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}
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if (crn == 13 && crm == 0) {
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if (opcode_2 == 0)
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return CP15[CP15_PID];
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if (opcode_2 == 1)
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return CP15[CP15_CONTEXT_ID];
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if (opcode_2 == 4)
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return CP15[CP15_THREAD_PRW];
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}
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if (crn == 15) {
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if (opcode_1 == 0 && crm == 12) {
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if (opcode_2 == 0)
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return CP15[CP15_PERFORMANCE_MONITOR_CONTROL];
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if (opcode_2 == 1)
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return CP15[CP15_CYCLE_COUNTER];
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if (opcode_2 == 2)
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return CP15[CP15_COUNT_0];
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if (opcode_2 == 3)
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return CP15[CP15_COUNT_1];
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}
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if (opcode_1 == 5 && opcode_2 == 2) {
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if (crm == 5)
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return CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS];
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if (crm == 6)
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return CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS];
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if (crm == 7)
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return CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE];
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}
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if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
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return CP15[CP15_TLB_DEBUG_CONTROL];
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}
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}
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LOG_ERROR(Core_ARM11, "MRC CRn={}, CRm={}, OP1={} OP2={} is not implemented. Returning zero.",
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crn, crm, opcode_1, opcode_2);
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return 0;
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}
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// Write to the CP15 registers. Used with implementation of the MCR instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) {
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if (InAPrivilegedMode()) {
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if (crn == 1 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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CP15[CP15_CONTROL] = value;
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else if (opcode_2 == 1)
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CP15[CP15_AUXILIARY_CONTROL] = value;
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else if (opcode_2 == 2)
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CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value;
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} else if (crn == 2 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
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CP15[CP15_TRANSLATION_BASE_TABLE_0] = value;
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else if (opcode_2 == 1)
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CP15[CP15_TRANSLATION_BASE_TABLE_1] = value;
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else if (opcode_2 == 2)
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CP15[CP15_TRANSLATION_BASE_CONTROL] = value;
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} else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) {
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CP15[CP15_DOMAIN_ACCESS_CONTROL] = value;
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} else if (crn == 5 && opcode_1 == 0 && crm == 0) {
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if (opcode_2 == 0)
|
|
CP15[CP15_FAULT_STATUS] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INSTR_FAULT_STATUS] = value;
|
|
} else if (crn == 6 && opcode_1 == 0 && crm == 0) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_FAULT_ADDRESS] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_WFAR] = value;
|
|
} else if (crn == 7 && opcode_1 == 0) {
|
|
if (crm == 0 && opcode_2 == 4) {
|
|
CP15[CP15_WAIT_FOR_INTERRUPT] = value;
|
|
} else if (crm == 4 && opcode_2 == 0) {
|
|
LOG_ERROR(Core_ARM11, "Unimplemented virtual to physical address");
|
|
} else if (crm == 5) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_INVALIDATE_INSTR_CACHE] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value;
|
|
else if (opcode_2 == 6)
|
|
CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value;
|
|
else if (opcode_2 == 7)
|
|
CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value;
|
|
} else if (crm == 6) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_INVALIDATE_DATA_CACHE] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
|
|
} else if (crm == 7 && opcode_2 == 0) {
|
|
CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value;
|
|
} else if (crm == 10) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_CLEAN_DATA_CACHE] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value;
|
|
} else if (crm == 14) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
|
|
}
|
|
} else if (crn == 8 && opcode_1 == 0) {
|
|
if (crm == 5) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_INVALIDATE_ITLB] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value;
|
|
} else if (crm == 6) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_INVALIDATE_DTLB] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value;
|
|
} else if (crm == 7) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_INVALIDATE_UTLB] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value;
|
|
else if (opcode_2 == 3)
|
|
CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value;
|
|
}
|
|
} else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) {
|
|
CP15[CP15_DATA_CACHE_LOCKDOWN] = value;
|
|
} else if (crn == 10 && opcode_1 == 0) {
|
|
if (crm == 0 && opcode_2 == 0) {
|
|
CP15[CP15_TLB_LOCKDOWN] = value;
|
|
} else if (crm == 2) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_PRIMARY_REGION_REMAP] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_NORMAL_REGION_REMAP] = value;
|
|
}
|
|
} else if (crn == 13 && opcode_1 == 0 && crm == 0) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_PID] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_CONTEXT_ID] = value;
|
|
else if (opcode_2 == 3)
|
|
CP15[CP15_THREAD_URO] = value;
|
|
else if (opcode_2 == 4)
|
|
CP15[CP15_THREAD_PRW] = value;
|
|
} else if (crn == 15) {
|
|
if (opcode_1 == 0 && crm == 12) {
|
|
if (opcode_2 == 0)
|
|
CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value;
|
|
else if (opcode_2 == 1)
|
|
CP15[CP15_CYCLE_COUNTER] = value;
|
|
else if (opcode_2 == 2)
|
|
CP15[CP15_COUNT_0] = value;
|
|
else if (opcode_2 == 3)
|
|
CP15[CP15_COUNT_1] = value;
|
|
} else if (opcode_1 == 5) {
|
|
if (crm == 4) {
|
|
if (opcode_2 == 2)
|
|
CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
|
else if (opcode_2 == 4)
|
|
CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
|
} else if (crm == 5 && opcode_2 == 2) {
|
|
CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value;
|
|
} else if (crm == 6 && opcode_2 == 2) {
|
|
CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value;
|
|
} else if (crm == 7 && opcode_2 == 2) {
|
|
CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value;
|
|
}
|
|
} else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) {
|
|
CP15[CP15_TLB_DEBUG_CONTROL] = value;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Unprivileged registers
|
|
if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) {
|
|
CP15[CP15_FLUSH_PREFETCH_BUFFER] = value;
|
|
} else if (crn == 7 && opcode_1 == 0 && crm == 10) {
|
|
if (opcode_2 == 4)
|
|
CP15[CP15_DATA_SYNC_BARRIER] = value;
|
|
else if (opcode_2 == 5)
|
|
CP15[CP15_DATA_MEMORY_BARRIER] = value;
|
|
} else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) {
|
|
CP15[CP15_THREAD_UPRW] = value;
|
|
}
|
|
}
|
|
|
|
void ARMul_State::ServeBreak() {
|
|
if (!GDBStub::IsServerEnabled()) {
|
|
return;
|
|
}
|
|
|
|
if (last_bkpt_hit && last_bkpt.type == GDBStub::BreakpointType::Execute) {
|
|
DEBUG_ASSERT(Reg[15] == last_bkpt.address);
|
|
}
|
|
|
|
DEBUG_ASSERT(system != nullptr);
|
|
Kernel::Thread* thread = system->Kernel().GetThreadManager().GetCurrentThread();
|
|
system->CPU().SaveContext(thread->context);
|
|
|
|
if (last_bkpt_hit || GDBStub::IsMemoryBreak() || GDBStub::GetCpuStepFlag()) {
|
|
last_bkpt_hit = false;
|
|
GDBStub::Break();
|
|
GDBStub::SendTrap(thread, 5);
|
|
}
|
|
}
|