panda !
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@@ -94,6 +94,7 @@ class GPU {
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void reset();
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Registers& getRegisters() { return regs; }
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ExternalRegisters& getExtRegisters() { return externalRegs; }
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void startCommandList(u32 addr, u32 size);
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// Used by the GSP GPU service for readHwRegs/writeHwRegs/writeHwRegsMasked
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@@ -396,7 +396,7 @@ void GPUService::flushCacheRegions(u32* cmd) {
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void GPUService::setBufferSwapImpl(u32 screenId, const FramebufferInfo& info) {
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using namespace PICA::ExternalRegs;
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constexpr static std::array<u32, 8> fb_addresses = {
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static constexpr std::array<u32, 8> fbAddresses = {
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Framebuffer0AFirstAddr,
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Framebuffer0BFirstAddr,
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Framebuffer1AFirstAddr,
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@@ -407,11 +407,13 @@ void GPUService::setBufferSwapImpl(u32 screenId, const FramebufferInfo& info) {
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Framebuffer1BSecondAddr,
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};
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const u32 fb_index = info.activeFb * 4 + screenId * 2;
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gpu.writeExternalReg(fb_addresses[fb_index], VaddrToPaddr(info.leftFramebufferVaddr));
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gpu.writeExternalReg(fb_addresses[fb_index + 1], VaddrToPaddr(info.rightFramebufferVaddr));
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auto& regs = gpu.getExtRegisters();
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constexpr static std::array<u32, 6> config_addresses = {
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const u32 fbIndex = info.activeFb * 4 + screenId * 2;
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regs[fbAddresses[fbIndex]] = VaddrToPaddr(info.leftFramebufferVaddr);
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regs[fbAddresses[fbIndex + 1]] = VaddrToPaddr(info.rightFramebufferVaddr);
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static constexpr std::array<u32, 6> configAddresses = {
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Framebuffer0Config,
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Framebuffer0Select,
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Framebuffer0Stride,
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@@ -420,10 +422,10 @@ void GPUService::setBufferSwapImpl(u32 screenId, const FramebufferInfo& info) {
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Framebuffer1Stride,
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};
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const u32 config_index = screenId * 3;
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gpu.writeExternalReg(config_addresses[config_index], info.format);
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gpu.writeExternalReg(config_addresses[config_index + 1], info.displayFb);
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gpu.writeExternalReg(config_addresses[config_index + 2], info.stride);
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const u32 configIndex = screenId * 3;
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regs[configAddresses[configIndex]] = info.format;
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regs[configAddresses[configIndex + 1]] = info.displayFb;
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regs[configAddresses[configIndex + 2]] = info.stride;
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}
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// Actually send command list (aka display list) to GPU
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